Knowledge Base

This article contains the following sections: 

• What is a Machine-Check Exception (MCE)?
• Understanding the machine-check architecture
• Decoding the machine-check exception
• Other considerations

What is a Machine-Check Exception (MCE)?

The machine check archetecture is a mechanism within the CPU to detect and report hardware issues. When a problem is detected a machine-check exception (#MC) is thrown. If a machine-check exception has been thrown and a purple screen fault occurs, a hardware problem has caused it. There is no other way to throw a machine-check exception.

Understanding the machine-check architecture

• MCG_CAP – a read-only register that provides information about the machine-check architecture implementation
• MCG_CTL – controls the reporting of machine-check exceptions
• MCG_STATUS – reports information when a machine-check exception occurs

• MCi_CTL – controls the reporting for the bank
• MCi_STATUS – contains the information about the machine-check exception
• MCi_ADDR – memory address of the exception (if deemed valid)
• MCi_MISC – additional description of the machine-check exception (if deemed valid)

• Bank 0 – Data Cache
• Bank 1 – Instruction Cache
• Bank 2 – Bus Unit
• Bank 3 – Load Store Unit
• Bank 4 – Northbridge and DRAM

Decoding the machine-check exception

Decoding the Global Status register (General Status) - MCG_STATUS

 

• Bits 63 > 3 – Reserved
• Bit 2 – MCIP – Machine check in progress
• Bit 1 – EIPV – Error IP valid flag
• Bit 0 – RIPV – Restart IP valid flag

Decoding the Bank Status registers (MCA only)

Simple Error Code Encoding

Compound Error Code Encoding

Note: In this example, you need to match 0000 1110 0000 1111 to Bus and Interconnect error, and decode the PP,T,RRRR,II and LL values.

Encoding of Request (RRRR) Sub-Field

Encodings of Participation (PP) Sub-Field

Example of decoding a bank status register 

1. Check to see who the CPU manufacturer is. 
   
   Run the following command:
   
   # cat /proc/cpuinfo
   
   The output shows a line with vendor_id.
   
   vendor_id       : GenuineIntel
   
   In this case the CPU manufacturer is Intel and thus, you are not able to determine the significance of the bank number. If it were AMD, the bank number provides more details.
   
   
2. You see from the log entry, the value of MC0_STATUS is be0000001008081f . This value is in hexadecimal. You must convert this 64bit number to binary to further decode this information.
   
   be0000001008081f = 1011 1110 0000 0000 0000 0000 0000 0000 0001 0000 0000 1000 0000 1000 0001 1111
   
   
3. Decode the 7 most significant bits first to see the general information contained within, that is, decode bits 57 - 63 which are 1011 111 .
   
   Bit 63 = 1 – MCi_STATUS register contents are valid (if this bit is 0, then ignore all of the data in this register)
   Bit 62 = 0 – An overflow did not occur
   Bit 61 = 1 – Error was not corrected
   Bit 60 = 1 – Error checking was enabled
   Bit 59 = 1 – Contents of the MCi_MISC register is valid
   Bit 58 = 1 – Contents of the MCi_ADDR register is valid
   Bit 57 = 1 – Processor context is corrupt - register values are unreliable
   
   Note: Bits are counted from 0 to 63, 0 being the least significant bit and 63 being the most significant bit.
   
   
4. Decode the MCA error code. The MCA error code is the 16 lowest significant bits of the MCi_STATUS register, that is, decode bits 0 - 15 which are 0000 1000 0001 1111.
   
   The pattern of these bits follows the complex error codes for bus and interconnect errors. The pattern is 0000 1PPT RRRR IILL.
   
   Decoding the pattern you get:
   
   0000 1000 0001 1111
   0000 1PPT RRRR IILL
   
   PP   =   00 –  Local processor was performing an operation that failed
   T    =    0 – Operation that was in progress did not time-out
   RRRR = 0001 – Operation was a generic read operation
   II   =   11 – Operation was marked as Other Transaction, that is, not a regular memory or I/O operation
   LL   =   11 – Generic level, or not a cache based operation
   
   
5. Summarize the findings:
   
   It seems as a fault occured during a generic read operation to either normal memory space or an I/O device.
   
   
6. Work on correcting any of the hardware issues. If required, contact the hardware vendor for further assistance.

Other considerations

• The information reported by the machine-check architecture is to aid in troubleshooting the hardware issue. Occasionally the information decoded from the MCA error code is not enough. If more information is required, refer to the documentation from the CPU manufacturers for more details. 
  
  
• If the information is invalid but a machine-check exception has occurred, it may be that a fault occurred where enough information regarding the fault could not be recorded. In this case a hardware issue is still at fault.
  
  
• Depending on the hardware fault, the vmware-log file for the failure may contain information for machine-check exceptions occurring for more than one CPU. Decoding the information reported by all CPUs may provide to be useful. 
  
  
• Providing the log entries containing the machine-check information to the hardware vendor may help with their investigation of the problems with the hardware.